Model for Predicting Fatigue Life of Nanomaterials

Model for Predicting jade action of Nano existentsIntroductionIn the sometime(prenominal), the primary go of micro-organizations incase was to provide input/output (I/O) friendships to and from ruffled circuits (ICs) and to provide interconnectedness in the midst of the comp championnts on the clay jury level while physically supporting the electronic device and protecting the assembly from the environment.In nine to maturation the meshality and the miniaturization of the current electronic devices, these IC devices check non only incorpo estimated more than transistors but bring in also include more active and passive comp match littlents on an individual head for the hills. This has sphereed in the emergent trend of a new convergent system1Currently, in that location atomic number 18 trinity trader(prenominal)(prenominal) approaches to achieving these convergent systems, namely the system-on- disrupt (SOC), system-in- case (SIP) and system on mailboat ( SOP). SOC seeks to commingle legion(predicate) system functions on sensation ti chip. However, this approach has numerous fundamental and economical limitations which include last fabrication costs and consolidation limits on wire little communications, which out-of-pocket to inherent losses of silicon and surface of it restriction.SIP is a 3-D advancement approach, where vertical stacking of multi-chip modules is employed. Since all of the ICs in the stack be still limited to CMOS IC treat, the fundamental desegregation limitation of the SOC still re mains. SOP on the differentwise hand, seeks to get hold of a richlyly incorpo rambled microminiaturized system on the package using silicon for transistor integrating and package for RF, digital and optical consolidation1 IC packaging is genius of the key enabling technologies for micro goor performance.As performance increments, technical challenges amplification in the studys of power deli precise, heat remova l, I/O density and thermo- mechanised dependability. These ar the most difficult challenges for improving performance and change magnitude integration, a ample with diminish manufacturing cost.Chip-to-package inter conjunctives in microsystems packages serve as galvanizing interconnections but often live on by mechanisms much(prenominal) as devolve and suck up. Furthermore, driven by the assume for growing the system functionality and decrease the feature coat, the International Technology Roadmap for Semi-conductors (ITRS) has predicted that integrate chip (IC) packages leave behind arrive interconnections with I/O tend of 90 nm by the year 2018 2. Lead-based solder cloths learn been used for interconnections in flip chip engineering science and the surface mount engine room for many an(prenominal) a(prenominal) decades.The traditional lead-based and lead-free solder bumps lead non satisfy the thermic machinelike requirement of these fine ripes interco nnects. These electronic packages, even under habitual operating conditions, send packing reach a temperature as senior gritty(prenominal) as one hundred fiftyC. Due to differences in the coefficient of thermic expansion of the reals in an IC package, the packages volition experience signifi locoweedt thermal manakins payable to the pair, which in turn leave cause lead and lead-free solder interconnections to get around prematurely.Aggarwal et al 3 had simulate the stock see by chip to package interconnect. In his work, he unquestionable interconnects with a visor of 15 to 50 micrometre on incompatible substrate using classic beam theory. compute 1 shows the stately of his model and a compendious of some of his passs.Although pliable intrerconect could visits the reach experience by the interconnect, it is still in comfortable. Chng et al. 4 performed a parametric study on the grind livelinesstime of a solder newspaper mainstay for a agitate of 10 0micrometre using a macro-micro approach. In her work, she veritable models of a solder column/bump with a pad coat of 50micrometre and top sides of 50 micrometre to two hundred micrometre. Table I shows a compend of some of her results.Table 1.1 sc ar off liveliness sentence estimation of solder columnchip thickness (micrometre)250640640640 tabular array CTE (ppm/K)1818105solder column height (micrometre)Fatigue conduct estimation/cycle)5081N.A1713237100 one hundred fifty272763124150134315184405cc74382735772It can be seen from Table 1.1 that the pall lives of all solder columns be passing short. Apart from the 5ppm/K board where on that point is excellent CTE matching, the largest deteriorate keeptime of the solder column is only about 518 cycles. As expected, the fatigue brio out harvest-festivals significantly when the board CTE decreases from 18ppm/K to 10ppm/K and as the height add-ons from 50micrometre to 200micrometre.This is generally out-of-pocket to th e large gunstock induced by the thermal mismatch as shown in conformation 1.2.The maximum inelastic principal focus was about 0.16 which exceeds the maximum gunstock that the genuine can support. Although the fatigue life of the chip to package interconnection can be increases by change magnitude the interconnects height, it will non be able to visit the laid-back absolute absolute frequency galvanizing requirements of the future IC where they compulsion to be operating at a high frequencies of 10-20 GHz and a signal bandwidth of 20 Gbps,By definition, nanocrystalline materials ar materials that have texture coat slight(prenominal) than 100nm and these materials argon not new since nanocrystalline materials have been observed in several naturally-occurring specimens including seashells, bone, and tooth enamel 5, 6. However, the nanocrystalline materials have been attr play acting a lot of inquiry interest cod to its superior mechanical and electrical properties as compargond to the coarse- iotaed counterpart.For example, the nano-crystalline tomentum has about 6 extension the forcefulness of bulk papal bull 7. Furthermore, the improvement in the mechanical properties due to the simplification in impress size of it has been intumesce(p)-documented. Increase in force play due to the lessening in cereal grass-size is predicted by the Hall-Petch relationship which has also been corroborate numerically by Swygenhoven et al 8 and was first demonstrated experimentally by Weertman 9.The implantation of nanocrystalline slob as interconnect materials seems to be feasible from the treat viewpoint too. Copper has been used as interconnects materials since 1989 whereas nano- strapper has also been widely care for using electroplating and other monstrous plastic deformation techniques in the past few years. For instance, Lu et al. 10 have describe electroplating of nano- dogshit with granulate size less than 100 nm and electrical con ductivity comparable to microcrystalline bulls eye. Furthermore, Aggarwal et al 11 have demonstrated the feasibility of using electrolytic plating processes to rely nanocrystalline nickel as a back-end wafer compatible process. However, in that respect are definite challenges regarding implantation of nanocrystalline squealer as interconnects materials.As discussed above, nanocrystalline hair have a high potential of being used as the next extension interconnect for electronic packaging. However, it is vital to understand their material properties, deformation mechanisms and microstructures stability. Although the increase in saturation due to the Hall-Petch relationship which has also been corroborate numerically and experimentally by Weertman 9, the improvement in the fatigue properties is not well documented and no model has been throwed to predict/characterize these nano materials in interconnection application conflicting results regarding the fatigue properties have also been inform. Kumar et al 12 reported that for nano-crystalline and ultra-fine crystalline Ni, although there is an increase in flexible striving range and the endurance limit, the bye ontogeny rate also increases.However, Bansal et al. 7 reported that with diminish instill size, the malleable tensity range increases but the click growth rate decreases substantially at the same cyclical line intensity range. Thus, nanostructured materials can potentially provide a solution for the dependability of low jactitate interconnections. However, the fatigue resistance of nanostructured interconnections needs to be and investigated.Since whit boundaries in polycrystalline material increases the total energy of the system as compare to perfect single crystal, it will resulted in a driving force to chasten the overall atom point of accumulation state by increasing the average food whit size. In the case of nanocrystalline materials which have a high mickle split up of tittle boundaries, there is a huge driving force for texture to growth and this presented a presents a significant obstacle to the processing and use of nanocrystalline sloven for interconnect applications.Millet et al 13 have shown, though a series of systematic molecular kinetics modelings, perforate growth in bulk nanocrystalline blur during annealing at constant temperature of 800K can be impeded with dopants segregated in the tittle boundaries regions. However, it has been observed that attempt can trigger atom growth in nanocrystalline materials 14 and there is no literature available on impeding stress assisted whit growth. There is an impending need to investigate the deterrent to grain growth caused by the dopant during fatigue/stress assisted grain growthDissertation ObjectivesThe goal of present project is to develop a model for the fatigue resistance of nano-materials that have been shown to have superior fatigue resistance. Accordingly, the undermentione d inquiry objectives are proposed.Develops a model for predicting fatigue life of nanostructured chip-to-package fuzz interconnectionsDevelops a fundamental understanding on the fatigue appearance of nanocrystalline copper for interconnect applicationAddresses the issue on the stability of nanocrystalline materials undergoing cyclic loadingOverview of the ThesisThe thesis is organized so that past research on nanocrystalline materials forms the basis of the understanding and new knowledge discovered in this research. Chapter 2 reviews much of the pertinent literature regarding nanocrystalline materials, including synthesis, deformation mechanisms, and grain growth.Chapter 3 describes a detailed overview of the technical aspects of the molecular kinetics pretence regularity including inter-atomic potentials, time integration algorithms, the NVT NPT, and NEPT ensembles, as well as periodic limit conditions and neighbor lists. Include in this chapter is the algorithms for creati ng nanocrystallinematerials used in this dissertations.. Chapter 4 describes the simulation procedure designed to investigate and develop the yearn crack growth analysis. The results of the long crack growth analysis will be presented at the end of Chapter 4. Chapter 5 presents the result and discussion on mechanical bearing of single and nanocrystalline copper contented to monotonic and cyclic loading whereas Chapter 6 presents the result and discussion on the obstructer to grain growth caused by the dopant during fatigue/stress assisted grain growth. Finally, conclusions and recommendations for future work are presented in Chapter 5.Chapter 2This chapter offers an expanded summary of the literature published with regards to the fabrication modes, characterization, and properties of nanocrystalline materials in sum total to a description of existing interconnect technology.2.1 Off-Chip Interconnect TechnologiesChip-to-package interconnections in microsystems packages serve as electrical interconnections but they will often failed by mechanisms much(prenominal) as fatigue and cower. Furthermore, driven by the need for increase the system functionality and decrease the feature size, the International Technology Roadmap for Semi-conductors (ITRS) has predicted that interconnections of integrated chip (IC) packages will have a I/O pitch of 90 nm by the year 2018 2.The International Technology Roadmap for Semiconductors (ITRS) roadmap is a roadmap that semiconducting material device industry closely follows closely and its projects the need for several technology generations. The package must be capable of happening these projections in devote for it to be successful. This section reviews some of the current interconnect technology.Wire bonding 15 as shown in look 2.1, is generally considered as one of the most simple, efficient and flexible interconnect technology. The devices on the silicon die are (gold or aluminum) wire bonded to electrically con nect from the chip to the wire bond pads on the periphery. However, the disadvantages of wire bonding are the slow rate, large pitch and long interconnect length and indeed this will not be adequate for high I/O application.Instead of wires in the wire bonding, taping automated bonding (TAB) is an interconnect technology using a prefabricated pierce polyimide film, with copper leads mingled with chip and substrate. The advantage of this technology is the high by dint ofput and the high lead count. However, it is limited by the high initial costs for tooling.An alternating(a) to peripheral interconnect technology is the area-array solution, as shown in act 2.3, that glide path the unused area by using the area under the chip. In area-array packaging, the chip has an array of solder bumps that are joined to a substrate. Under-fill is consequently fills the gap between the chip and substrate to enhance mechanical adhesion. This technology gives the highest packaging density rules and best electrical propertys of all the avaiable interconnection technology. However, not only is its initial cost is high, it requires a in truth demanding technology to progress and operate.With the need for higher(prenominal) I/O density, conformable interconnects have been developed to satisfy the mechanical requirements of high performance micron sized interconnects. The underlying idea is to curtail shear stress experienced by the interconnects through increasing their height or decreasing of its shear modulus (i.e. increases in their nonresistant) and indeed the name pliant interconnects. Some of recent research in compliant interconnects include Tesseras all-inclusive Area Vertical Expansion, Form Factors Wire on Wafer and Georgia Institute of Technologys Helix interconnects 17-19 as shown in Figure 2.4.Although compliant interconnects can solve the problem of mechanical reliability issue, they are through with(p) at the expense of the electrical performanc e. Since there is a need to tighten the packages parasitic through a decrease line delays, there is a need to minimize the electrical connection length in piece to increase the system working frequency. Hence, compliant interconnect may not meet the high electrical frequency requirements of future devices.Figure 2.4 (a) wide Area Vertical Expansion, (b) Wire on Wafer and (c) G-Helix 17-19Lead and lead-free solders typically fail mechanical when scaled down to less than to a pitch of 100 mm. Compliant interconnections, on the other hand, do not meet the high frequency electrical requirements. The Microsystems Packaging Research Center at Georgia institute of Technology had demonstrated the feasibility of using re-workable nanostructure interconnections. Aggarwal et al 20 had show that nanostructured nickel interconnections, through a Flip Chip probe vehicle, was able to improve the mechanical reliability while maintaining the shor rill electrical connection length. However, the m ain disadvantages of this manner was the significant signal loss at high frequency signal of nanocrystalline nickel 21.As discussed above, nanostructure interconnects technology is the most brilliant interconnect technology to best meet the stringent mechanical and electrical requirement of next generation devices. However, there is a need of an thumb materials and a sensible choice of materials in this case would be nanocrystalline copper for its high peculiarity material with superior electrical conductivity.Hence, it would be just to use nanocrystalline-copper as material for the nanostructure interconnects. Due to the tendency for the grain to grow, there is a need to stabilize the grain growth in nanocrystalline copper before using it could be considered as a potential view for nanostructure interconnect.2.2 Nanocrystalline materialNanocrystalline materials are polycrystalline materials with an average grain size of less than 100 nm 22. Over the past decade , new nanocrys talline or nanostructured materials with key microstructural length scales on the coiffe of a few tens of nanometers has been gaining a lot of interest in the material science research society.This is generally due to its unique and superior properties, as compared to their microcrystalline counterparts which includes increased military posture 22 and wear resistance 23. These unique properties are due to the large bulk component of atoms at or near the grain boundaries. As a result, these materials have unique properties that are phonation of both the grain barrier surface device characteristics and the bulk. youthful advances in synthesis and processing systemology for producing nanocrystalline materials such as inert gas condensation 24, mechanical milling 25, 26, electro- stupefyion 27, and double-dyed(a) plastic deformation 28 have made it affirmable to produce decent nanocrystalline materials for miniscule scale application.2.2.1 SynthesisInert gas condensation, the first rule used to synthesis bulk nanocrystalline 29, consists of evaporating a metal inside a high- nullity chamber and thus backfilling the chamber with inert gas 30. These evaporated metal atoms would whence collide with the gas atoms, causing them to lose kinetic energy and condenses into pulverisation of trivial nano-crystals. These pulverises are consequently compacted under high pressure and make clean into nearly fully dense nanocrystalline solids.The grain size distribution obtained from this method is unremarkably very narrow. However, the major draws back of this method are its high porosity levels and imperfection bonding. Grain coarsening also occurs due to the high temperature during the calf love stage 31.Mechanical milling consists of heavy cyclic deformation in powders until the final composition of the powders corresponds to a real percentages of the respective initial constituents 25, 26. A wide grain size distribution is obtained by this method. Thi s technique is a popular method to prepare nanocrystalline materials because of its pertinence to any material and simplicity. However, their main drawback includes contamination and grain coarsening during the consolidation stage.Electro-deposition consists of using electrical current to reduce cations of a desired material from a electrolyte solution and coating a conductive object on the substrate. Electro-deposition has many advantages over processing techniques and this includes its applicability to a wide variety of materials, low initial capital enthronisation requirements and porosity-free finished products without a need for consolidation processing 27. Furthermore, Shen et al. 32 and Lu et al.33 had lately show that the right electro-deposition condition can produce a passing twinned structure which leads to enhanced ductility. The main drawback of this method is it is the difficulty to strive high purity.Severe plastic deformation, such as high-pressure torsion, fit ted channel angular extrusion (ECAE), continuous confined shear torturing and accumulative roll-bonding, uses extreme plastic origining to produce nanocrystalline materials by mechanisms such as grain fragmentation, dynamic recovery, and geometric re-crystallization 34. It is the only technology that modify conventional macro-grained metals directly into nanocrystalline materials without the need of potentially hazardous nano-sized powders. This is achieved by introducing very high shear deformations into the material under superimposed hydrostatic pressure. twain of the most commonly used methods are high-pressure torsion and ECAE 35. In the study of the effect of ECAE on the microstructure of nanocrystalline copper, Dalla Torre et al 36 observed that the grains become more equi-axial and randomly orientation as the number of passes increases, as shown in Figure 2.5Figure 2.5 Microstructure of ECAE copper subjected to (a) 1 passes (b) 2 passes (c) 4 passes (d) 8 passes (e) 12 p asses and (f) 16 passes 362.2.2 Mechanical Behavior of nanocrystalline materialsDue to the small grain size and high masses fraction of grain boundaries, nanocrystalline materials exhibit significantly contrastive properties and expression as compared to their microcrystalline counterpart. The structure and mechanical expression of nanocrystalline materials has been the subject of a lot of researchers interests both experimentally 37-43 and theoretically 44-50. This section reviews the principal mechanical properties and behavior of nanocrystalline materials.2.2.2.1 Strength and ductility novel studies of nanocrystalline metals have shown that there is a five to ten fold increases in the position and gracelessness as compared to their microcrystalline state 7, 36, 37, 51, 52. This increase in the dexterity is due to the nominal head of grain boundaries impeding the nucleation and movement of disruptions.Since decreasing grain spring size increases the number of barrier and the amount of applied stress indispensable to move a kerfuffle across a grain limit point, this resulted in a much higher allot strength. The inverse relationship between grain size and strength is characterized by the Hall-Petch relationship 53, 54 as shown in equation (2.1).Eq (2.1)In equation (2.1), s is the mechanical strength, k is a material constant and d is the average grain size. Hence, nanocrystalline materials are expected to exhibit higher strength as compared to their microcrystalline counterpart. Figure 2.6 and Figure 2.7 show the summary of cogency and generate strength from tensile test that are reported in the literature. Indeed, insensibility and yield strength of copper with a grain size of 10nm (3GPa) can be one order higher than their microcrystalline counterpart. To the larger specimens.Derivation from Hall-Petch relationship begins as the grain size approaches 30nm where the stresses needed to activate the dislocation multiplication via Frank-Read sour ces at heart the grains are too high and the plastic deformation is instead accommodated by grain boundaries sliding and migration.12. Furthermore, as the grain size reduces, the hoi polloi fraction of the grain boundaries and the triple points increases.Material properties will be more exemplification of the grain bounce activity 64 and this will resulting the strength to be reciprocally proportional to grain size instead of square roots of the grain size as predicted by Hall Petch relation 65. Further reduction in the grain size will result in grain boundaries processes controlling the plastic deformation and reverse Hall-Petch effect, where the materials soften, will take place.Although precedent defects had been account for the earlier experimental observation of reverse Hall-Petch effect24, Swygenhoven et al 66 and Schiotz et al 47, using molecular simulation, was able to showed that nanocrystalline copper had the highest strength (about 2.3GPa ) at a grain size of 8nm and 10-15nm respectively. Conrad et al 67 pointed out that below this critical grain size, the mechanisms shifted to grain boundary-mediated from dislocation-mediated plasticity and this causes the material to become dependent on push rate, temperature, Taylor orientation factor and strawman of the type of dislocation.The yield stress of nanocrystalline copper was passing sensitive to change shape rate even though it is a fcc materials. The tinge rate esthesia, m, in equation 2.2 a engineering contention which measured the dependency of the strain rate and Figure 2.8 shows a summary of m as a function of grain size for copper specimen in the literature 51, 68-70. Due to high localized dislocation activities at the grain boundaries which results in enhanced strain rate sensitivities in nanocrystalline materials, m increases drastically when the grain size is below 0.1 mm as shown in Figure 2.8.(2.2)Room temperature strain rate aesthesia was effect to dependent on dislocation ac tivities and grain boundaries diffusion 52, 71, 72. Due to the miserable lattice diffusion at get on temperature, the rate limiting process for microcrystalline copper was the gliding dislocation to cutting through timber dislocation, resulting in low strain rate sensitivities.However, due to the increasing figurehead of obstacles such as grain boundaries for nanocrystalline materials, the rate limiting process for smaller grain size was the interaction of dislocation and the grain boundaries, which is strain rate and temperature dependence. By considering the length scale of the dislocation and grain boundaries interaction, Cheng et al 52 proposed the next model for strain rate sensitivities. (2.3)z is the distance swept by the dislocation during activation, r is the dislocation density and a, a and b are the proportional factors. With this model, they will be able to predict higher strain rate sensitivities for nanocrystalline material produced by severe plastic deformation as compared to other technique. Since the twin boundaries in nanocrystalline or ultra fine grain copper served as a barriers for dislocation motion and nucleation which led to passing localized dislocations near the twin boundaries, the strain rate sensitivity of copper with high density of coherent twin boundaries was set up to be higher than those without any twin boundaries 33. Lastly, the increase enhanced strain rate sensitivity in nanocrystalline copper had been ascribe for it increases in strength and ductility. For example, Valiev et al 60 credit the enhanced strain rate sensitivity of 0.16 for the high ductility.In growth to a strong dependency on the strain rate, strength in nanocrystalline materials was also highly dependent on the temperature. Wang et al 73 observed that the yield strength for ultra fine grain copper with a grain size of 300nm increases from approximately 370MPa to 500MPa when the temperature reduces from room temperature to 77k. The authors attribu ted this increase in yield strength due to the absence of additional thermal deformation processes at 77k. This is uniform with Huang et al 74 observation where the temperature dependence of nanocrystalline copper with an increase in cruelness of nanocrystalline copper with lowering the temperature is notedDuctility is another important characteristic of nanocrystalline materials. In microcrystalline materials, a reduction in grain size will increase the ductility due to the charge of grain boundaries acting as effective barriers to the propagation of micro-cracks75. However, nanocrystalline copper showed a lower strain to failure than that of their microcrystalline counterparts and this lacks in ductility was attributed to the presence of processing defects 76.Recent advanced in processing of nanocrystalline materials offer materials with fairly good ductility in additional to ultra-high strength. Lu et al 10 reported that nanocrystalline copper with stripped-down flaw produced via electro-deposition had an elongation to fracture of 30%. Furthermore, Youssef et al 77 observed a 15.5% elongation to failure for defect free nanocrystalline copper produced via mechanical milling. Hence, it was doable for nanocrystalline copper to be both strong and ductile if the processing artifacts are minimized.The failure are ordinarily consists of dimples several time larger than their grain size was median(prenominal)ly found on the failure morphology of nanocrystalline materials and Kumar et al 78 presented the following model for initiation and hence the eventual failure of nanocrystalline materials. Furthermore, the presence of shear region was found to be due to shear fixing since the ratio of strain hardening rate to prevailing stress was usually small 79, 80.Figure 2.9 Schematic illustration of fracture in nanocrystalline material postulated by Kumar et al 782.2.2.2 CreepsNanocrystalline materials are expected to creep during room temperature. This is because Due to the higher fraction of grain boundaries and triple junctions, self diffusivity of nanocrystalline material had been shown to increase by an order of tercet as compared to microcrystalline copper 81. Since creep behavior was dependent on grain size and diffusivity, with creep rate increases with an increase in diffusivity or a decrease in grain size, the creep temperature for nanocrystalline copper was known to be a small fraction of melting temperature (about 0.22 of its melting points). Furthermore, since creep had always been cited as one of the reason for grain size softening in nanocrystalline materials, creeps were other important mechanical properties of nanocrystalline materials that had been gaining a lot of researchers attention.Due to the high volume fraction of grain boundaries and enhanced diffusivity rateModel for Predicting Fatigue Life of NanomaterialsModel for Predicting Fatigue Life of NanomaterialsIntroductionIn the past, the primary function of micro-syste ms packaging was to provide input/output (I/O) connections to and from integrated circuits (ICs) and to provide interconnection between the components on the system board level while physically supporting the electronic device and protecting the assembly from the environment.In order to increase the functionality and the miniaturization of the current electronic devices, these IC devices have not only incorporated more transistors but have also include more active and passive components on an individual chip. This has resulted in the emerging trend of a new convergent system1Currently, there are three main approaches to achieving these convergent systems, namely the system-on-chip (SOC), system-in-package (SIP) and system on package (SOP). SOC seeks to integrate numerous system functions on one silicon chip. However, this approach has numerous fundamental and economical limitations which include high fabrication costs and integration limits on wireless communications, which due to inherent losses of silicon and size restriction.SIP is a 3-D packaging approach, where vertical stacking of multi-chip modules is employed. Since all of the ICs in the stack are still limited to CMOS IC processing, the fundamental integration limitation of the SOC still remains. SOP on the other hand, seeks to achieve a highly integrated microminiaturized system on the package using silicon for transistor integration and package for RF, digital and optical integration1 IC packaging is one of the key enabling technologies for microprocessor performance.As performance increases, technical challenges increase in the areas of power delivery, heat removal, I/O density and thermo-mechanical reliability. These are the most difficult challenges for improving performance and increasing integration, along with decreasing manufacturing cost.Chip-to-package interconnections in microsystems packages serve as electrical interconnections but often fail by mechanisms such as fatigue and creep. Furt hermore, driven by the need for increase the system functionality and decrease the feature size, the International Technology Roadmap for Semi-conductors (ITRS) has predicted that integrated chip (IC) packages will have interconnections with I/O pitch of 90 nm by the year 2018 2. Lead-based solder materials have been used for interconnections in flip chip technology and the surface mount technology for many decades.The traditional lead-based and lead-free solder bumps will not satisfy the thermal mechanical requirement of these fine pitches interconnects. These electronic packages, even under normal operating conditions, can reach a temperature as high as 150C. Due to differences in the coefficient of thermal expansion of the materials in an IC package, the packages will experience significant thermal strains due to the mismatch, which in turn will cause lead and lead-free solder interconnections to fail prematurely.Aggarwal et al 3 had modeled the stress experienced by chip to pack age interconnect. In his work, he developed interconnects with a height of 15 to 50 micrometre on assorted substrate using classic beam theory. Figure 1 shows the conventional of his model and a summary of some of his results.Although compliant intrerconect could reduces the stress experienced by the interconnect, it is still in sufficient. Chng et al. 4 performed a parametric study on the fatigue life of a solder column for a pitch of 100micrometre using a macro-micro approach. In her work, she developed models of a solder column/bump with a pad size of 50micrometre and heights of 50 micrometre to 200 micrometre. Table I shows a summary of some of her results.Table 1.1 Fatigue life estimation of solder columnchip thickness (micrometre)250640640640board CTE (ppm/K)1818105solder column height (micrometre)Fatigue life estimation/cycle)5081N.A171323710015027276312415013431518440520074382735772It can be seen from Table 1.1 that the fatigue lives of all solder columns are passing shor t. Apart from the 5ppm/K board where there is excellent CTE matching, the largest fatigue life of the solder column is only about 518 cycles. As expected, the fatigue life increases significantly when the board CTE decreases from 18ppm/K to 10ppm/K and as the height increases from 50micrometre to 200micrometre.This is in the first place due to the large strain induced by the thermal mismatch as shown in Figure 1.2.The maximum inelastic principal strain was about 0.16 which exceeds the maximum strain that the material can support. Although the fatigue life of the chip to package interconnection can be increases by increasing the interconnects height, it will not be able to meet the high frequency electrical requirements of the future IC where they need to be operating at a high frequencies of 10-20 GHz and a signal bandwidth of 20 Gbps,By definition, nanocrystalline materials are materials that have grain size less than 100nm and these materials are not new since nanocrystalline mat erials have been observed in several naturally-occurring specimens including seashells, bone, and tooth enamel 5, 6. However, the nanocrystalline materials have been attracting a lot of research interest due to its superior mechanical and electrical properties as compared to the coarse-grained counterpart.For example, the nano-crystalline copper has about 6 time the strength of bulk copper 7. Furthermore, the improvement in the mechanical properties due to the reduction in grain size has been well-documented. Increase in strength due to the reduction in grain-size is predicted by the Hall-Petch relationship which has also been confirmed numerically by Swygenhoven et al 8 and was first demonstrated experimentally by Weertman 9.The implantation of nanocrystalline copper as interconnect materials seems to be feasible from the processing viewpoint too. Copper has been used as interconnects materials since 1989 whereas nano-copper has also been widely treat using electroplating and oth er severe plastic deformation techniques in the past few years. For instance, Lu et al. 10 have reported electroplating of nano-copper with grain size less than 100 nm and electrical conductivity comparable to microcrystalline copper. Furthermore, Aggarwal et al 11 have demonstrated the feasibility of using electrolytic plating processes to deposit nanocrystalline nickel as a back-end wafer compatible process. However, there are certain challenges regarding implantation of nanocrystalline copper as interconnects materials.As discussed above, nanocrystalline copper have a high potential of being used as the next generation interconnect for electronic packaging. However, it is vital to understand their material properties, deformation mechanisms and microstructures stability. Although the increase in strength due to the Hall-Petch relationship which has also been confirmed numerically and experimentally by Weertman 9, the improvement in the fatigue properties is not well documented an d no model has been established to predict/characterize these nano materials in interconnection application conflicting results regarding the fatigue properties have also been reported. Kumar et al 12 reported that for nano-crystalline and ultra-fine crystalline Ni, although there is an increase in tensile stress range and the endurance limit, the crack growth rate also increases.However, Bansal et al. 7 reported that with decreasing grain size, the tensile stress range increases but the crack growth rate decreases substantially at the same cyclic stress intensity range. Thus, nanostructured materials can potentially provide a solution for the reliability of low pitch interconnections. However, the fatigue resistance of nanostructured interconnections needs to be bring forward investigated.Since grain boundaries in polycrystalline material increases the total energy of the system as compare to perfect single crystal, it will resulted in a driving force to reduce the overall grain b oundary area by increasing the average grain size. In the case of nanocrystalline materials which have a high volume fraction of grain boundaries, there is a huge driving force for grain to growth and this presented a presents a significant obstacle to the processing and use of nanocrystalline copper for interconnect applications.Millet et al 13 have shown, though a series of systematic molecular dynamics simulations, grain growth in bulk nanocrystalline copper during annealing at constant temperature of 800K can be impeded with dopants segregated in the grain boundaries regions. However, it has been observed that stress can trigger grain growth in nanocrystalline materials 14 and there is no literature available on impeding stress assisted grain growth. There is an impending need to investigate the impediment to grain growth caused by the dopant during fatigue/stress assisted grain growthDissertation ObjectivesThe goal of present project is to develop a model for the fatigue resist ance of nano-materials that have been shown to have superior fatigue resistance. Accordingly, the following research objectives are proposed.Develops a model for predicting fatigue life of nanostructured chip-to-package copper interconnectionsDevelops a fundamental understanding on the fatigue behavior of nanocrystalline copper for interconnect applicationAddresses the issue on the stability of nanocrystalline materials undergoing cyclic loadingOverview of the ThesisThe thesis is organized so that past research on nanocrystalline materials forms the basis of the understanding and new knowledge discovered in this research. Chapter 2 reviews much of the pertinent literature regarding nanocrystalline materials, including synthesis, deformation mechanisms, and grain growth.Chapter 3 describes a detailed overview of the technical aspects of the molecular dynamics simulation method including inter-atomic potentials, time integration algorithms, the NVT NPT, and NEPT ensembles, as well as periodic boundary conditions and neighbor lists. Include in this chapter is the algorithms for creating nanocrystallinematerials used in this dissertations.. Chapter 4 describes the simulation procedure designed to investigate and develop the long crack growth analysis. The results of the long crack growth analysis will be presented at the end of Chapter 4. Chapter 5 presents the result and discussion on mechanical behavior of single and nanocrystalline copper subjected to monotonic and cyclic loading whereas Chapter 6 presents the result and discussion on the impediment to grain growth caused by the dopant during fatigue/stress assisted grain growth. Finally, conclusions and recommendations for future work are presented in Chapter 5.Chapter 2This chapter offers an expanded summary of the literature published with regards to the fabrication methods, characterization, and properties of nanocrystalline materials in addition to a description of existing interconnect technology.2.1 Off- Chip Interconnect TechnologiesChip-to-package interconnections in microsystems packages serve as electrical interconnections but they will often failed by mechanisms such as fatigue and creep. Furthermore, driven by the need for increase the system functionality and decrease the feature size, the International Technology Roadmap for Semi-conductors (ITRS) has predicted that interconnections of integrated chip (IC) packages will have a I/O pitch of 90 nm by the year 2018 2.The International Technology Roadmap for Semiconductors (ITRS) roadmap is a roadmap that semiconductor industry closely follows closely and its projects the need for several technology generations. The package must be capable of meeting these projections in order for it to be successful. This section reviews some of the current interconnect technology.Wire bonding 15 as shown in Figure 2.1, is generally considered as one of the most simple, cost-efficient and flexible interconnect technology. The devices on the si licon die are (gold or aluminum) wire bonded to electrically connect from the chip to the wire bond pads on the periphery. However, the disadvantages of wire bonding are the slow rate, large pitch and long interconnect length and hence this will not be able for high I/O application.Instead of wires in the wire bonding, tape automated bonding (TAB) is an interconnect technology using a prefabricated perforated polyimide film, with copper leads between chip and substrate. The advantage of this technology is the high throughput and the high lead count. However, it is limited by the high initial costs for tooling.An ersatz to peripheral interconnect technology is the area-array solution, as shown in Figure 2.3, that adit the unused area by using the area under the chip. In area-array packaging, the chip has an array of solder bumps that are joined to a substrate. Under-fill is then fills the gap between the chip and substrate to enhance mechanical adhesion. This technology gives th e highest packaging density methods and best electrical characteristics of all the avaiable interconnection technology. However, not only is its initial cost is high, it requires a very demanding technology to establish and operate.With the need for higher I/O density, compliant interconnects have been developed to satisfy the mechanical requirements of high performance micron sized interconnects. The introductory idea is to reduce shear stress experienced by the interconnects through increasing their height or decreasing of its shear modulus (i.e. increases in their compliant) and hence the name compliant interconnects. Some of recent research in compliant interconnects include Tesseras Wide Area Vertical Expansion, Form Factors Wire on Wafer and Georgia Institute of Technologys Helix interconnects 17-19 as shown in Figure 2.4.Although compliant interconnects can solve the problem of mechanical reliability issue, they are through at the expense of the electrical performance. Since there is a need to reduce the packages parasitic through a decrease line delays, there is a need to minimize the electrical connection length in order to increase the system working frequency. Hence, compliant interconnect may not meet the high electrical frequency requirements of future devices.Figure 2.4 (a) Wide Area Vertical Expansion, (b) Wire on Wafer and (c) G-Helix 17-19Lead and lead-free solders typically fail mechanical when scaled down to less than to a pitch of 100 mm. Compliant interconnections, on the other hand, do not meet the high frequency electrical requirements. The Microsystems Packaging Research Center at Georgia institute of Technology had demonstrated the feasibility of using re-workable nanostructure interconnections. Aggarwal et al 20 had show that nanostructured nickel interconnections, through a Flip Chip test vehicle, was able to improve the mechanical reliability while maintaining the shortest electrical connection length. However, the main disadvantag es of this method was the significant signal loss at high frequency signal of nanocrystalline nickel 21.As discussed above, nanostructure interconnects technology is the most bright interconnect technology to best meet the stringent mechanical and electrical requirement of next generation devices. However, there is a need of an assemble materials and a sensible choice of materials in this case would be nanocrystalline copper for its high strength material with superior electrical conductivity.Hence, it would be expert to use nanocrystalline-copper as material for the nanostructure interconnects. Due to the tendency for the grain to grow, there is a need to stabilize the grain growth in nanocrystalline copper before using it could be considered as a potential campaigner for nanostructure interconnect.2.2 Nanocrystalline materialNanocrystalline materials are polycrystalline materials with an average grain size of less than 100 nm 22. Over the past decade , new nanocrystalline or na nostructured materials with key microstructural length scales on the order of a few tens of nanometers has been gaining a lot of interest in the material science research society.This is generally due to its unique and superior properties, as compared to their microcrystalline counterparts which includes increased strength 22 and wear resistance 23. These unique properties are due to the large volume fraction of atoms at or near the grain boundaries. As a result, these materials have unique properties that are representative of both the grain boundary surface characteristics and the bulk.Recent advances in synthesis and processing methodology for producing nanocrystalline materials such as inert gas condensation 24, mechanical milling 25, 26, electro-deposition 27, and severe plastic deformation 28 have made it possible to produce sufficient nanocrystalline materials for small scale application.2.2.1 SynthesisInert gas condensation, the first method used to synthesis bulk nanocryst alline 29, consists of evaporating a metal inside a high-vacuum chamber and then backfilling the chamber with inert gas 30. These evaporated metal atoms would then collide with the gas atoms, causing them to lose kinetic energy and condenses into powder of small nano-crystals. These powders are then compacted under high pressure and vacuum into nearly fully dense nanocrystalline solids.The grain size distribution obtained from this method is usually very narrow. However, the major draws back of this method are its high porosity levels and imperfection bonding. Grain coarsening also occurs due to the high temperature during the press stage 31.Mechanical milling consists of heavy cyclic deformation in powders until the final composition of the powders corresponds to a certain percentages of the respective initial constituents 25, 26. A wide grain size distribution is obtained by this method. This technique is a popular method to prepare nanocrystalline materials because of its applic ability to any material and simplicity. However, their main drawback includes contamination and grain coarsening during the consolidation stage.Electro-deposition consists of using electrical current to reduce cations of a desired material from a electrolyte solution and coating a conductive object on the substrate. Electro-deposition has many advantages over processing techniques and this includes its applicability to a wide variety of materials, low initial capital enthronisation requirements and porosity-free finished products without a need for consolidation processing 27. Furthermore, Shen et al. 32 and Lu et al.33 had late show that the right electro-deposition condition can produce a highly twinned structure which leads to enhanced ductility. The main drawback of this method is it is the difficulty to achieve high purity.Severe plastic deformation, such as high-pressure torsion, equal channel angular extrusion (ECAE), continuous confined shear push and accumulative roll-bo nding, uses extreme plastic straining to produce nanocrystalline materials by mechanisms such as grain fragmentation, dynamic recovery, and geometric re-crystallization 34. It is the only technology that modify conventional macro-grained metals directly into nanocrystalline materials without the need of potentially hazardous nano-sized powders. This is achieved by introducing very high shear deformations into the material under superimposed hydrostatic pressure. dickens of the most commonly used methods are high-pressure torsion and ECAE 35. In the study of the effect of ECAE on the microstructure of nanocrystalline copper, Dalla Torre et al 36 observed that the grains become more equi-axial and randomly orientation as the number of passes increases, as shown in Figure 2.5Figure 2.5 Microstructure of ECAE copper subjected to (a) 1 passes (b) 2 passes (c) 4 passes (d) 8 passes (e) 12 passes and (f) 16 passes 362.2.2 Mechanical Behavior of nanocrystalline materialsDue to the small g rain size and high volume fraction of grain boundaries, nanocrystalline materials exhibit significantly contrary properties and behavior as compared to their microcrystalline counterpart. The structure and mechanical behavior of nanocrystalline materials has been the subject of a lot of researchers interests both experimentally 37-43 and theoretically 44-50. This section reviews the principal mechanical properties and behavior of nanocrystalline materials.2.2.2.1 Strength and ductilityRecent studies of nanocrystalline metals have shown that there is a five to ten fold increases in the strength and hardness as compared to their microcrystalline state 7, 36, 37, 51, 52. This increase in the strength is due to the presence of grain boundaries impeding the nucleation and movement of dislocations.Since decreasing grain boundary size increases the number of barrier and the amount of applied stress demand to move a dislocation across a grain boundary, this resulted in a much higher yield strength. The inverse relationship between grain size and strength is characterized by the Hall-Petch relationship 53, 54 as shown in equation (2.1).Eq (2.1)In equation (2.1), s is the mechanical strength, k is a material constant and d is the average grain size. Hence, nanocrystalline materials are expected to exhibit higher strength as compared to their microcrystalline counterpart. Figure 2.6 and Figure 2.7 show the summary of hardness and yield strength from tensile test that are reported in the literature. Indeed, hardness and yield strength of copper with a grain size of 10nm (3GPa) can be one order higher than their microcrystalline counterpart. To the larger specimens.Derivation from Hall-Petch relationship begins as the grain size approaches 30nm where the stresses needed to activate the dislocation multiplication via Frank-Read sources at heart the grains are too high and the plastic deformation is instead accommodated by grain boundaries sliding and migration.12. Furthe rmore, as the grain size reduces, the volume fraction of the grain boundaries and the triple points increases.Material properties will be more representative of the grain boundary activity 64 and this will resulting the strength to be mutually proportional to grain size instead of square roots of the grain size as predicted by Hall Petch relation 65. Further reduction in the grain size will result in grain boundaries processes controlling the plastic deformation and reverse Hall-Petch effect, where the materials soften, will take place.Although example defects had been account for the earlier experimental observation of reverse Hall-Petch effect24, Swygenhoven et al 66 and Schiotz et al 47, using molecular simulation, was able to showed that nanocrystalline copper had the highest strength (about 2.3GPa ) at a grain size of 8nm and 10-15nm respectively. Conrad et al 67 pointed out that below this critical grain size, the mechanisms shifted to grain boundary-mediated from dislocatio n-mediated plasticity and this causes the material to become dependent on strain rate, temperature, Taylor orientation factor and presence of the type of dislocation.The yield stress of nanocrystalline copper was highly sensitive to strain rate even though it is a fcc materials. The strain rate sensitivity, m, in equation 2.2 a engineering parametric quantity which measured the dependency of the strain rate and Figure 2.8 shows a summary of m as a function of grain size for copper specimen in the literature 51, 68-70. Due to high localized dislocation activities at the grain boundaries which results in enhanced strain rate sensitivities in nanocrystalline materials, m increases drastically when the grain size is below 0.1 mm as shown in Figure 2.8.(2.2)Room temperature strain rate sensitivity was found to dependent on dislocation activities and grain boundaries diffusion 52, 71, 72. Due to the trifling lattice diffusion at room temperature, the rate limiting process for microcrysta lline copper was the gliding dislocation to cutting through woodwind dislocation, resulting in low strain rate sensitivities.However, due to the increasing presence of obstacles such as grain boundaries for nanocrystalline materials, the rate limiting process for smaller grain size was the interaction of dislocation and the grain boundaries, which is strain rate and temperature dependence. By considering the length scale of the dislocation and grain boundaries interaction, Cheng et al 52 proposed the following model for strain rate sensitivities. (2.3)z is the distance swept by the dislocation during activation, r is the dislocation density and a, a and b are the proportional factors. With this model, they will be able to predict higher strain rate sensitivities for nanocrystalline material produced by severe plastic deformation as compared to other technique. Since the twin boundaries in nanocrystalline or ultra fine grain copper served as a barriers for dislocation motion and nuc leation which led to highly localized dislocations near the twin boundaries, the strain rate sensitivity of copper with high density of coherent twin boundaries was found to be higher than those without any twin boundaries 33. Lastly, the increase enhanced strain rate sensitivity in nanocrystalline copper had been credited for it increases in strength and ductility. For example, Valiev et al 60 credited the enhanced strain rate sensitivity of 0.16 for the high ductility.In addition to a strong dependency on the strain rate, strength in nanocrystalline materials was also highly dependent on the temperature. Wang et al 73 observed that the yield strength for ultra fine grain copper with a grain size of 300nm increases from approximately 370MPa to 500MPa when the temperature reduces from room temperature to 77k. The authors attributed this increase in yield strength due to the absence of additional thermal deformation processes at 77k. This is tenacious with Huang et al 74 observation where the temperature dependence of nanocrystalline copper with an increase in hardness of nanocrystalline copper with lowering the temperature is notedDuctility is another important characteristic of nanocrystalline materials. In microcrystalline materials, a reduction in grain size will increase the ductility due to the presence of grain boundaries acting as effective barriers to the propagation of micro-cracks75. However, nanocrystalline copper showed a lower strain to failure than that of their microcrystalline counterparts and this lacks in ductility was attributed to the presence of processing defects 76.Recent advanced in processing of nanocrystalline materials offer materials with fairly good ductility in additional to ultra-high strength. Lu et al 10 reported that nanocrystalline copper with borderline flaw produced via electro-deposition had an elongation to fracture of 30%. Furthermore, Youssef et al 77 observed a 15.5% elongation to failure for defect free nanocrystall ine copper produced via mechanical milling. Hence, it was possible for nanocrystalline copper to be both strong and ductile if the processing artifacts are minimized.The failure are usually consists of dimples several time larger than their grain size was normally found on the failure morphology of nanocrystalline materials and Kumar et al 78 presented the following model for initiation and hence the eventual failure of nanocrystalline materials. Furthermore, the presence of shear region was found to be due to shear hole since the ratio of strain hardening rate to prevailing stress was usually small 79, 80.Figure 2.9 Schematic illustration of fracture in nanocrystalline material postulated by Kumar et al 782.2.2.2 CreepsNanocrystalline materials are expected to creep during room temperature. This is because Due to the higher fraction of grain boundaries and triple junctions, self diffusivity of nanocrystalline material had been shown to increase by an order of three as compared to microcrystalline copper 81. Since creep behavior was dependent on grain size and diffusivity, with creep rate increases with an increase in diffusivity or a decrease in grain size, the creep temperature for nanocrystalline copper was known to be a small fraction of melting temperature (about 0.22 of its melting points). Furthermore, since creep had always been cited as one of the reason for grain size softening in nanocrystalline materials, creeps were other important mechanical properties of nanocrystalline materials that had been gaining a lot of researchers attention.Due to the high volume fraction of grain boundaries and enhanced diffusivity rate